This invention relates generally to a semiconductor apparatus, such as a SRAM operating at a lower supply voltage.
A semiconductor memory includes a writing operation control circuit, which control writing operation of digital data to a plurality of memory cells. Recently, it is required to design a semiconductor memory having both low power consumption and higher speed operation characteristics. In order to increase operating speed of a memory, threshold voltages Vth of MOS transistors should be lowered. However, when threshold voltages Vth of MOS transistors are lowered, leak current of the MOS transistors is increased.
Accordingly, an object of the present invention is to provide a writing operation control circuit, in which operating speed can be improved and at the same time leak current of MOS transistors can be decreased.
Another object of the present invention is to provide a semiconductor memory having an improved writing operation control circuit, in which operating speed can be improved and at the same time leak current of MOS transistors can be decreased.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
According to a first aspect of the present invention, a writing operation control circuit for a semiconductor memory includes a write control terminal, to which a write controlling signal indicating enable or disable of writing is supplied; a writing data terminal, to which a writing data signal is supplied; a driving circuit which operates to perform a writing operation in response to the writing data signal, the driving circuit having a specific threshold voltage; a first voltage control circuit which selectively outputs first and second supply voltages to the driving circuit in response to a logical level of the write controlling signal; and a second voltage control circuit which selectively outputs third and fourth supply voltages to the driving circuit in response to a logical level of the write controlling signal. The second supply voltage is higher than the first supply voltage, the first supply voltage is higher than the fourth supply voltage, the fourth supply voltage is higher than the third supply voltage.
According to a second aspect of the present invention, a semiconductor memory includes a plurality of memory cells each of which store digital data; and a writing operation control circuit connected to the plurality of memory cells. The writing operation control circuit for a semiconductor memory includes a write control terminal, to which a write controlling signal indicating enable or disable of writing is supplied; a writing data terminal, to which a writing data signal is supplied; a driving circuit which operates to perform a writing operation in response to the writing data signal, the driving circuit having a specific threshold voltage; a first voltage control circuit which selectively outputs first and second supply voltages to the driving circuit in response to a logical level of the write controlling signal; and a second voltage control circuit which selectively outputs third and fourth supply voltages to the driving circuit in response to a logical level of the write controlling signal. The second supply voltage is higher than the first supply voltage, the first supply voltage is higher than the fourth supply voltage, the fourth supply voltage is higher than the third supply voltage.